Device and method for test computer

ABSTRACT

A test device for testing startup performance of a computer comprises a setting circuit for recording triggering times for triggering startup of the computer and a time interval between two successive startups of the computer, a monolithic chip ( 10 ) comprising an input pin connected to the setting circuit, and an output pin for connection to the computer, the input pin being configured for receiving signals containing therein from the setting circuit, the output pin being configured for sending a computer startup signal, at the time interval, to the computer in response to the received signals; and a display device ( 20 ) electronically connected with the monolithic chip, the display device being configured for displaying at least one of the triggering times and the time interval.

BACKGROUND

1. Field of the Invention

The present invention relates to test devices and methods, and moreparticularly to a test device and method for testing startup performanceof a computer.

2. Description of Related Art

After a computer is produced, quality tests are required. One of thetests is for testing startup performance of the computer. In testing,the computer is powered on and off repeatedly.

A conventional test involves connecting the computer to an AC powersupply, and then powering it on and off by controlling the AC powersupply. However, the AC power supply has a complicated configuration andis expensive. When many computers need testing, many AC power suppliesare required.

What is needed, therefore, is a test device with simple structure andmethod that automatically controls the computers to be powered on andoff repeatedly.

SUMMARY

A test device for testing startup performance of a computer comprises asetting circuit for recording triggering times for triggering startup ofthe computer and a time interval between two successive startups of thecomputer, a monolithic chip comprising an input pin connected to thesetting circuit, and an output pin for connection to the computer, theinput pin being configured for receiving signals containing therein fromthe setting circuit, the output pin being configured for sending acomputer startup signal, at the time interval, to the computer inresponse to the received signals; and a display device electronicallyconnected with the monolithic chip, the display device being configuredfor displaying at least one of the triggering times and the timeinterval. A method for testing startup performance of a computer,comprising the steps of: providing a test device, determining triggeringtimes for triggering startup of the computer and a time interval betweentwo successive startups of the computer, inputting the triggering timesand the time interval into the setting circuit, causing the monolithicchip to run in a sleeping state if the triggering times is equal tozero, sending a startup triggering signal from the monolithic chip tothe computer, if the triggering times is greater than zero and the timeinterval is elapsed, and then reducing the triggering times by one.

Other advantages and novel features will be drawn from the followingdetailed description of preferred embodiments with attached drawings, inwhich:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a testing device in accordance with apreferred embodiment of the present invention; and

FIG. 2 is a flow chart of a working process of a system using amonolithic chip in accordance with a preferred embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE EMBODIMENT

Referring to FIG. 1, a testing device in accordance with a preferredembodiment of the present invention includes a monolithic chip 10, aseven-segment LED display 20, and a setting circuit.

The seven-segment LED display 20 includes three seven-segment lightemitting diodes (LEDs). The seven-segment LED display 20 has threeindividual digits. The seven-segment LED display 20 includes sevencathodes a-g and three common anodes bs1-bs3. The three common anodesbs1-bs3 of the seven-segment LED display 20 are connected respectivelyto three collectors of three PNP transistors Q2, Q3, Q4. Three emittersof the PNP transistors Q2, Q3, Q4 are commonly connected to a voltagesource V2.

The setting circuit includes three button switches S1, S2, S3 and threediodes D1, D2, D3. Each button switch includes a first terminal and asecond terminal. The first terminals of the button switches S1, S2, S3are connected respectively to positive terminals of the diodes D1, D2,D3. The negative terminals of the diodes D1, D2, D3 are connectedrespectively to three bases of the PNP transistors Q2, Q3, Q4 via threeresistors R51-R53.

A detailed description of a relationship between the chip 10 and othercircuits follows:

The monolithic chip 10 is an MCF0504 microcontroller, which includesseven output pins R00-R06, three pins R10-R12, a pin R33, a pin R34, apair of pins VDD, VSS, and a pin R35.

The seven output pins R00-R06 are connected respectively to the sevencathodes a-g of the seven-segment LED display 20.

The three pins R10-R12 are connected respectively to the negativeterminals of the diodes D1, D2, D3 for sending out a low level signalabout 2 milliseconds in turn repeatedly to enable the seven segment LEDsto work in turn, in viewing the LEDs it will seem they are always onbecause of the rapidity of the flashing of the LEDs. For example, whenthe pin RIO sends out a low level signal, the base of the PNP transistorQ2 is at low level, thereby turning on the PNP transistor Q2. Thus, theanode bs1 of the corresponding seven-segment LED is at high level toenable the corresponding seven-segment LED to work.

The pin 33 is connected to the second terminals of the button switchesS1, S2, S3. Normally, the pin R33 is at a high level. When one buttonswitch is pressed, the pin R33 will receive a signal from the one buttonswitch, and the monolithic chip 10 will identify which button switch ispressed. For example, a momentary press of the button switch S1 willenable the pin R33 at low level due to the low voltage level between twoterminals of the diode D1.

The pin R34 is connected to a base of an NPN transistor Q1. An emitterof the NPN transistor Q1 is connected to ground. A collector of the NPNtransistor Q1 is connected to a voltage source V1 via a resistor R48 andto an output terminal O. The output terminal O is connected to thecomputer to send a signal to the computer for controlling the computerto startup/shut down. The pin R34 alternately sends out a high levelsignal and a low level signal. When the pin R34 sends out a high levelsignal, the NPN transistor Q1 is turned on. Thus, the output terminal Osends out a low level signal to trigger the computer to startup/shutdown.

The pins VDD, VSS are connected respectively to input terminals I1, I2.The input terminals I1, I2 are connected respectively to a positiveterminal and a negative terminal of a power supply.

The pin R35 is connected to a reset circuit. The reset circuit includesa button switch S4 and a capacitor C. The pin R35 is connected to oneterminal of the button switch S4 and one terminal of the capacitor C.The other terminal of the button switch S4 and the other terminal of thecapacitor C are connected to ground. The pin R35 is also connected tothe voltage source V1 via a resistor R41. The monolithic chip 10 isreset when the button switch S4 is triggered.

Before test, the number of times and the time intervals need to be setby pressing the button switches S1, S2, S3.

The button switch S1 is used for selecting test parameters by triggeringthe button switch S1. The button switch S2 is used for setting the valueof selected test parameter. The button switch S3 is used for enteringthe setting value to be saved in the monolithic chip 10. The testparameters include a number of times (between 0 and 600) and timeintervals (between 0 and 60 minutes). The time intervals are set inminutes. A momentary press of the button switch S1 will switch thecurrent display to a number of times setting mode. After the number oftimes has been set, a momentary press of the button switch S1 willswitch the display into the time intervals setting mode. When the numberof times mode is selected, each momentary press of the button switch S2will increment the displayed number by one. After the value of ones hasbeen set, a momentary press of the button switch S3 enters the settingvalue to be saved in the monolithic chip 10. After that, each momentarypress of the button switch S2 will increment the displayed number by 10.After the value of tens has been set, a momentary press of the buttonswitch S3 enters the setting value to be saved in the monolithic chip10. Lastly, each momentary press of the button switch S2 will incrementthe displayed number by 100. After the value of tens has been set, amomentary press of the button switch S3 enters the setting value to besaved in the monolithic chip 10. Then pressing S1 again will switch thedisplay to time interval mode and the process as above is followed toset the time interval.

Referring also to FIG. 2, the working process of a system using themonolithic chip 10 includes a plurality of steps as follows:

Step 1: initializing the monolithic chip 10;

Step 2: the system checking if the number of times is equal to zero. Ifthe number of times is equal to zero, the system enters a sleepingstate; if the number of times is not equal to zero, the system starts upa timing function therein;

Step 3: the system checking if a predetermined test interval has elapsedif the number of test times is not equal to zero. If the predeterminedtest interval is over, the monolithic chip outputs a high level signalto turn on the NPN transistor Q1 and the output terminal O outputs a lowlevel signal to the computer to power on/off the computer. After that,the system reduces the testing times by one and the system returns tothe step 2; if the predetermined test interval is not over, the systemreturns to the step 3.

It is to be understood, however, that even though numerouscharacteristics and advantages have been set forth in the foregoingdescription of preferred embodiments, together with details of thestructures and functions of the preferred embodiments, the disclosure isillustrative only, and changes may be made in detail, especially inmatters of shape, size, and arrangement of parts within the principlesof the invention to the full extent indicated by the broad generalmeaning of the terms in which the appended claims are expressed.

1. A test device for testing startup performance of a computer,comprising: a setting circuit for recording triggering times fortriggering startup of the computer and a time interval between twosuccessive startups of the computer; a monolithic chip comprising aninput pin connected to the setting circuit, and an output pin forconnection to the computer, the input pin being configured for receivingsignals containing therein from the setting circuit, the output pinbeing configured for sending a computer startup signal, at the timeinterval, to the computer in response to the received signals; and adisplay device electronically connected with the monolithic chip, thedisplay device being configured for displaying at least one of thetriggering times and the time interval.
 2. The test device as describedin claim 1, wherein the display device comprises a plurality ofseven-segment LEDs, the plurality of seven-segment LEDs comprising sevenfirst terminals, the monolithic chip comprising seven pins connected tothe seven input terminals of the display device configured forcontrolling the display device, each of the seven-segment LEDs having asecond common terminal connected to a corresponding pin of themonolithic chip.
 3. The test device as described in claim 2, furthercomprising a switch device, wherein each of the second common terminalsof the seven-segment LED is connected to the corresponding pin of themonolithic chip via the switch device.
 4. The test device as describedin claim 3, wherein the switch device is a PNP transistor, a collectorof the PNP transistor is connected to the corresponding second commonterminal, an emitter of the PNP transistor is connected to a voltagesource, and a base of the PNP transistor is connected to thecorresponding pin of the monolithic chip.
 5. The test device asdescribed in claim 4, wherein the setting circuit comprises a pluralityof button switches for manually inputting the triggering times and thetime interval, and each button switch has a first terminal connected toa pin of the monolithic chip for receiving signals from the settingcircuit.
 6. The test device as described in claim 5, wherein each buttonswitch has a second terminal connected to the selecting pin of themonolithic chip.
 7. The test device as described in claim 6, wherein apositive terminal of a diode is connected to the second terminal of eachbutton switch and a negative terminal of the diode is connected to theselecting pin of the monolithic chip.
 8. The test device as described inclaim 1, further comprising a switch device, wherein the output pin ofthe monolithic chip is connected to a control terminal of the switchdevice, the switch device having a first terminal connected to a voltagesource via a resistor and to an output terminal connected to thecomputer, the switch device having a second terminal connected toground, the monolithic chip being configured for sends a computerstartup signal to the computer via the switch device.
 9. The test deviceas described in claim 8, wherein the switch device is an NPN transistor,the first terminal of the switch device is a collector of the NPNtransistor, the second terminal of the switch device is an emitter ofthe NPN transistor, and the control terminal of the switch device is abase of the NPN transistor.
 10. The test device as described in claim 1,further comprising a reset circuit with the monolithic chip connectedthereto, wherein the reset circuit comprises a switch device and acapacitor, and a first terminal of the switch device and a firstterminal of the capacitor are connected to the monolithic chip and asecond terminal of the switch device and a second terminal of thecapacitor are connected to ground, the first terminals of the switchdevice and the capacitor are connected to a voltage source via aresistor.
 11. The test device as described in claim 1, wherein themonolithic chip is an MCF0504 chip.
 12. A method for testing startupperformance of a computer, comprising the steps of: providing a testdevice as described in claim 1; determining triggering times fortriggering startup of the computer and a time interval between twosuccessive startups of the computer; inputting the triggering times andthe time interval into the setting circuit; causing the monolithic chipto run in a sleeping state if the triggering times is equal to zero;sending a startup triggering signal from the monolithic chip to thecomputer, if the triggering times is greater than zero and the timeinterval is elapsed, and then reducing the triggering times by one.